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Silicon Labs /MGM240SA22VNA /MODEM_NS /SICTRL2

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Interpret as SICTRL2

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/MODEM_S/SICTRL2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SIRSTAGCMODE)SIRSTAGCMODE 0 (SIRSTPRSMODE)SIRSTPRSMODE 0 (SIRSTCCAMODE)SIRSTCCAMODE 0SUPERCHIPTHRESH 0 (DISSIFRAMEDET)DISSIFRAMEDET 0 (AGCRSTUPONSI)AGCRSTUPONSI

Description

No Description

Fields

SIRSTAGCMODE

SI reset by AGC
SIRSTPRSMODE

SI reset by PRS PAEN
SIRSTCCAMODE

SI reset by CCA req
SUPERCHIPTHRESH

Superchip pass threshold
DISSIFRAMEDET

Disable SI when framedet
AGCRSTUPONSI

AGC reset on SI reset

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data